1. Technical Field
The present invention is directed to a process for fabricating an integrated circuit device with a multilevel interconnect structure that has capacitors in the multilevel interconnect structure.
2. Art Background
Dynamic random access memory (DRAM) relates to electronic devices consisting of cells which can retain information only for a limited time before they must be read and refreshed at periodic intervals. A typical DRAM cell consists of at least one transistor and a storage capacitor. In general, the integrated circuit used for DRAMs consists of metal oxide semiconductor (MOS) and particularly complementary MOS structure (CMOS) as the transistor component. Recently, the capacity of such DRAM structures has evolved from one megabit to on the order of one gigabit. This increase in memory has required the evolution of gate feature sizes on the order of 1.25 microns down to on the order of 0.25 microns or smaller. As the DRAM capacity requirements are increased, the requirements placed on the capacitors are increased as well. Not only is there a requirement for increased capacitance, there is also a requirement for decreased capacitor area. Accordingly, development efforts have been focused on materials and structures to meet this need.
To minimize interconnection resistance and to maximize the use of valuable chip area, advanced VLSI and ULSI logic integrated semiconductor circuits use multi-level wiring line structures for interconnecting regions within the devices and for interconnecting one or more devices within the integrated circuit. Multi-level metallization provides greater flexibility in circuit design, a reduction in die size and, thereby, a reduction in chip cost. In fabricating such structures, the conventional approach is to form lower level wiring lines (or interconnect structures) and then form one or more upper level wiring lines interconnected with the first level wiring lines. A first level interconnect structure may be in contact with the doped region within the substrate of an integrated circuit device (for example the source or drain of a typical MOSFET). One or more interconnections are typically formed between the first level interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device. This is accomplished through the second and subsequent levels of wiring lines. Conductive vias are used to make the connection from one level to another. Metal layer (Mxe2x88x921) at the first level is connected to the source formed in the substrate layer of the integrated circuit. This metal layer Mxe2x88x921 is used to make electrical connections at level one as well as at higher levels using the described via structure.
An embedded DRAM structure adds integrated capacitors to the logic transistors to add high density memory cells to the circuit. These integrated capacitors can be connected to the source metallization of the MOS device to form the memory cell. Conventional DRAM capacitors often have a layer of polycrystalline silicon (polysilicon hereinafter) as the bottom electrode; a layer of silicon dioxide or silicon nitride as the insulator; and a top metal or polysilicon layer forming the top electrode. Such a structure is generally not compatible with embedded DRAM technology because of the added complexity of the polysilicon capacitors and the high temperatures required to grow the silicon oxide/nitride layer. For example, the aluminum metal layers used as interconnects in the multi-layer structure can be adversely affected by the relatively high temperatures used in the deposition of polysilicon and the formation of associated capacitor oxides. Furthermore, the use of polysilicon as an electrode can have deleterious affects on the electrical characteristics of the device. To this end, it is known to use tantalum pentoxide as the dielectric of the capacitor because of its higher dielectric constant compared to silicon dioxide or silicon nitride. During the chemical vapor deposition used to form the tantalum pentoxide, a necessary barrier layer is formed between the polysilicon layer and the tantalum pentoxide layer to prevent reduction of the tantalum pentoxide, and the leakage current that would result. Frequently, this barrier layer is a dielectric material such as silicon nitride. Dielectric materials used for these barrier layers typically have a dielectric constant lower than that of tantalum pentoxide. As can be appreciated, such barrier layer materials are not desired in a capacitor, as they tend to adversely impact the capacitance of the capacitor.
Accordingly, it is advantageous if the bottom plate of the capacitor is not required to be polysilicon. If the capacitors are formed in the interconnect layer instead of the device layer, the bottom plate of the capacitor can be metal instead of polysilicon. A method of forming a trench capacitor in an interconnect layer is disclosed in U.S. Serial No. 60/115520 which was filed on Jan. 12, 1999 and is commonly assigned with the present application. U.S. Serial No. 60/115520 discloses a method that requires chemical mechanical polishing of the interconnect structure after the metal for the top plate of the capacitor is backfilled into the capacitor trench. Such a step is complex because it requires planarization of the entire interconnect structure (including all previously formed interconnects) after the trench capacitors are formed. The method also requires that a resist-etchback process be used to recess the lower electrode into the via to withstand the planarization process. Such a process is time-consuming in that it requires the formation of a photoresist layer than resides only in the lower portion of the trench to selectively process (i.e. etch, deposit, etc.) the barrier on the sidewalls of the via. As such, the photoresist layer is not deposited in the upper portion (i.e. about the upper twenty-five percent) of the trench or on the horizontal surface of the wafer. In any process for device fabrication, it is advantageous if the number of such steps is kept to a minimum.
Accordingly, methods for forming trench capacitors in an interconnect layer continue to be sought.
The present invention is directed to process for semiconductor device fabrication. In the process, a trench is first formed in a dielectric layer in which metal interconnects have previously been formed. This dielectric layer is referred to as the interconnect layer. The dielectric layer is formed over an underlying layer that is either another interconnect layer or, in the embodiment wherein the interconnect layer is a first level metal interconnect layer, a device layer. The interconnects are electrically connected to metal in the underlying layer. The trench is formed so that it overlies a metal interconnect in the underlying layer. The trench is formed through the dielectric thickness, so the metal in the underlying layer is at the bottom of the trench. The trench is formed using conventional lithographic techniques. The width of the trench is selected so that the subsequently formed bottom plate of the capacitor will contact the metal underlying the trench.
After the trench is formed, an insulating sidewall spacer is formed on the sides of the trench to protect against possible contact to other conductors and to ensure that the bottom plate of the capacitor is in electrical contact with the underlying metal interconnect. The insulating barrier layer is deposited by chemical vapor deposition. Examples of suitable barrier materials include silicon dioxide and silicon nitride. These materials are deposited by plasma enhanced chemical vapor deposition, followed by an etchback to form the sidewall spacers.
After the layer of barrier material is formed on the trench sidewalls, the bottom plate of the capacitor is formed. The bottom plate is formed by depositing a blanket layer of metal on the interconnect layer. The thickness of the layer is selected to ensure that, after anisotropically etching the metal layer to remove the metal from the horizontal surface of the dielectric layer, the metal that remains in the trench is in electrical contact with the metal at the bottom of the trench. One skilled in the art is able to select the trench width, sidewall spacer thickness and metal layer thickness required to meet this objective.
For example, the trench size is selected to provide sufficient surface area for the capacitor to hold an adequate amount of charge for the particular application. Since the objective of a trench capacitor is to provide a capacitor that has a large surface area without using a commensurate amount of wafer surface area, some of the trench capacitor surface area is in the direction of the trench walls. In order to meet this objective, the thicknesses of the bottom plate metal conductor layer and the capacitor dielectric layer are selected to ensure that the metal covers the sidewalls of the trench, but does not fill up the trench. This ensures that the capacitor dielectric and the top plate of the capacitor will also be deposited in the trench. One skilled in the art will appreciate that these thicknesses, within the parameters described above, are largely a matter of design choice. For example, one skilled in the art may select thicknesses that will provide a particular topography that is advantageous based upon downstream processing requirements.
The metal layer is then etched to remove the metal that is formed on the top, horizontal surface of the interconnect layer. The metal that remains in the trench after the etch has a tapered configuration. That is, the metal layer is thinner at the top of the trench than at the bottom of the trench. After the etch, the thickness of the metal layer at the bottom of the trench is such that it contacts the metal that underlies the trench.
Expedients for etching metal are well known to one skilled in the art. The selected etch expedient removes the metal anisotropically, to ensure that there is metal remaining on the trench sidewalls after the metal on the surface of the interconnect layer has been removed. Metal that remains in the bottom of the trench adds to the capacitor surface area.
A layer of dielectric material is then formed on the interconnect layer. Since the bottom plate of the capacitor is a metal instead of conductive polycrystalline silicon, suitable dielectric materials include metal oxides in addition to dielectric materials (e.g. silicon dioxide) that are compatible with polycrystalline silicon capacitor plates. One example of a suitable dielectric material is tantalum pentoxide (Ta2O5). The thickness of the Ta2O5 layer is chosen to provide a relatively high capacitance (i.e., a capacitance greater than 20 fF) per cell yet maintain a relatively low leakage current (i.e., a leakage current less than 10 fF) per cell. A 10 nm-thick Ta2O5 layer meets these objectives.
The dielectric layer is first passivated with a layer of barrier material. The dielectric layer is then patterned by selectively removing the dielectric materials and associated barrier from over the metal interconnects previously formed in the interconnect layer. The dielectric layer is patterned using conventional lithography in which a mask is formed on the structure. The mask is patterned such that only the regions of the dielectric that overlie the previously formed metal interconnects are exposed through the mask. Conventional expedients for removing dielectric materials (e.g. a plasma etch) are used to removed these portions of the dielectric layer. The mask is then removed.
The remainder of the top plate of the capacitor is then formed. The top plate of the capacitor is completed by depositing an additional layer of metal on the substrate. The additional material layer has a thickness chosen to protect the underlying dielectric layer (in this example, Ta2O5) during subsequent processing. The thickness is also selected to be compatible with other portions of the integrated circuit (e.g. the logic portion). The metal layer can actually be multiple layers (e.g. alternating layers of barrier materials and metal such as TiN/Ti/TiN/Al/TiN). The initial layers of TiN of this multilayer structure are selected to conform to the trench configuration. The upper layers (i.e. the Ti/TiN/Al/TiN layers) have a thickness selected to ensure that, when completely formed, the trench is entirely filled by the capacitor. The metal is patterned to form the top plate of the capacitor and the interconnect lines of the logic portion of the integrated circuit. The metal is patterned using conventional lithographic techniques well known to one skilled in the art. The present invention is advantageous because the capacitors are fabricated without disturbing the underlying active devices. Furthermore, the process of the present invention is advantageous because it integrates well with the process for masking the active devices underlying the capacitors.